1. Field of the Invention
The present invention relates to a PLL (phase locked loop) circuit. The present invention further relates to a wireless device including the PLL circuit.
2. Description of Related Art
(First Conventional Configuration)
FIG. 13 is a block diagram showing a PLL circuit with a first conventional configuration. The PLL circuit in FIG. 13 includes a voltage controlled oscillator 10, a frequency divider 31, a first phase comparator 40, a reference signal input terminal 50, a charge pump 60, and a filter 70.
An operation of the PLL circuit with the above-described configuration will be described with reference to FIG. 13.
The frequency divider 31 divides an oscillation signal (fVCO) of the voltage controlled oscillator 10 at such a dividing ratio that the oscillation signal has the same frequency as that of a reference signal (fREF) input from the reference signal input terminal 50 to the first phase comparator 40. The first phase comparator 40 outputs a phase difference between a divided oscillation signal (fDIV) output from the frequency divider 31 and fREF input from the reference signal input terminal 50. The charge pump 60 converts the output signal of the first phase comparator 40 into a signal suitable for control of the voltage controlled oscillator 10. The filter 70 allows a DC component of the output signal of the charge pump 60 to pass therethrough so as to apply a control voltage to the voltage controlled oscillator 10. The voltage controlled oscillator 10 oscillates at a frequency (fVCO) in accordance with the control voltage output from the filter 70. An oscillation signal output from the voltage controlled oscillator 10 is input to the frequency divider 31, followed by the repetition of the above-described operation.
By repeated cycles of the above-described operation, when fDIV output from the frequency divider 31 is matched with fREF input from the reference signal input terminal 50, the PLL circuit is locked.
In FIG. 14, (a) is a characteristic diagram showing a change of the oscillation frequency fVCO with time in the PLL circuit shown in FIG. 13, and (b) is a characteristic diagram showing a change of a current iDIV of the frequency divider 31 with time. In FIG. 14, a vertical axis in (a) represents the oscillation frequency (fVCO) of the voltage controlled oscillator 10, and a vertical axis in (b) represents the current (iDIV) of the frequency divider 31. A timing tE on a horizontal axis is a timing at which the PLL circuit is locked. In FIG. 14, fL, fH, fLL, fHH, and fE on the vertical axis in (a) represent a lower limit operation frequency, an upper limit operation frequency, a frequency (fL−margin), a frequency (fH+margin), and a lock frequency, respectively, of the voltage controlled oscillator 10, and ifL, ifH, ifLL, and ifHH on the vertical axis in (b) represent currents necessary for the frequency divider 31 to divide the frequency at the set dividing ratio in the cases where fVCO is fL, fH, fLL, and fHH, respectively. In general, the frequency divider requires a larger current to divide a higher frequency. As shown in (a) in FIG. 14, an oscillation frequency range of the voltage controlled oscillator 10 is set with margins provided in addition to an operation range taking into consideration manufacturing variations of the PLL circuit, temperature fluctuations after the PLL circuit is locked, power supply voltage fluctuations, and the like.
As shown in FIG. 14, in the PLL circuit shown in FIG.13, since the oscillation frequency may reach fHH, the frequency divider 31 requires the current ifHH.
(Second Conventional Configuration)
FIG. 15 is a block diagram showing a PLL circuit with a second conventional configuration. The PLL circuit in FIG. 15 includes a voltage switching device 80 and a second phase comparator 92 in addition to the components of the PLL circuit shown in FIG. 13. FIG. 16 is a diagram showing an example of specific configurations of a voltage controlled oscillator 11 and the voltage switching device 80 as components of the PLL circuit in FIG. 15.
An operation of the PLL circuit with the above-described configuration will be described with reference to FIGS. 15 and 16.
The second phase comparator 92 averages a phase difference (frequency difference) between fDIV and fREF with respect to time, and outputs a control signal when the phase difference between fDIV and fREF is adjusted within a predetermined range. The voltage switching device 80 switches a voltage to be applied to the voltage controlled oscillator 11 in accordance with the signal output from the second phase comparator 92.
As shown in FIG. 16, the voltage switching device 80 includes a variable capacitor voltage output terminal 801, a control input terminal 802, a constant-voltage supply 803, a charge pump voltage input terminal 804, and a switch 805. The control input terminal 802 is connected to the output of the second phase comparator 92. The charge pump voltage input terminal 804 is connected to an output of the filter 70.
The switch 805 is connected to a constant-voltage supply 803 side at the start of adjustment of fVCO (during a coarse adjustment period), and then is connected to a charge pump voltage input terminal 804 side after the phase difference between fDIV and fREF is adjusted within the predetermined range (during a fine adjustment period). A voltage V0 or VCP selected by the switch 805 is output from the variable capacitor voltage output terminal 801.
As shown in FIG. 16, the voltage controlled oscillator 11 includes a variable capacitor voltage input terminal 111, a capacitor 112, a variable capacitor 113, switches 114a, 114b, and 114c, capacitors 115a, 115b, and 115c, an inductor 116, an oscillation circuit 117, and an oscillation signal output terminal 118.
During the coarse adjustment period, V0 is applied to the variable capacitor voltage input terminal 111, so that the variable capacitor 113 has a fixed capacitance determined by V0. By switching the switches 114a, 114b, and 114c selectively, the capacitors 115a, 115b, and 115c can be operated selectively so as to change a capacitance value discretely.
During the fine adjustment period, VCP is applied to the variable capacitor voltage input terminal 111. Accordingly, the variable capacitor 113 has a capacitance determined by VCP, and the capacitance value is changed continuously.
The PLL circuit shown in FIG. 15 is operated in a manner different from that of the PLL circuit shown in FIG. 13 in that the second phase comparator 92 switches between the coarse adjustment period and the fine adjustment period so as to adjust the frequency, followed by a lock of the PLL circuit. Although fVCO is unstable during the coarse adjustment period, a coarse adjustment can be made without a malfunction of the PLL circuit because the second phase comparator 92 outputs the time-averaged phase difference between fDIV and fREF.
FIG. 17 is a characteristic diagram showing a change of an oscillation frequency in the PLL circuit shown in FIG. 15. In FIG. 17, fS on a vertical axis represents a frequency at the start of the coarse adjustment, and tC on a horizontal axis represents a timing of finishing the coarse adjustment. The other symbols are the same as those in FIG. 14, and thus their descriptions will be omitted. As shown in FIG. 17, the frequency is adjusted discretely until the timing tC, and then the frequency is adjusted continuously after the timing tC. The PLL circuit is locked at a timing tE.
In the PLL circuit shown in FIG. 15, the frequency divider 31 requires the current ifHH as in the PLL circuit shown in FIG. 13. Such a configuration is used to obtain a wide oscillation frequency range, and is described in Patent document 1 (Japanese Patent No. 3488180), for example.
As shown in FIGS. 14 and 17, in each of the PLL circuits shown in FIGS. 13 and 15, in order for the frequency divider 31 to perform a normal dividing operation at the oscillation frequency fHH, the current ifHH is required, which is larger than the current iFH required at the upper limit operation frequency fH.
Further, since the PLL circuit shown in FIG. 15 is suitable for forming a capacitor and an inductor on a single semiconductor substrate, all the components can be included in a semiconductor integrated circuit. In such a case, it is difficult to adjust values of the capacitor and the inductor that determine the oscillation frequency after the formation of the semiconductor integrated circuit. On this account, margins to be provided in addition to an operation frequency range as shown in FIG. 17 have to be set larger than those shown in FIG. 14. As a result, the current ifHH becomes larger.
In recent years, the upper limit operation frequency is becoming higher due to the development of broadband wireless communication, and accordingly it is increasingly required to reduce the margins to be provided in addition to the operation frequency range.
When a wireless device including the PLL circuit that requires a large current as shown in FIG. 13 or 15 is operated by being powered through a battery, it is difficult to operate the wireless device for a long time since the PLL circuit consumes a large amount of power. To operate the wireless device for a long time, a larger battery may be prepared, which, however, brings about another problem in that it becomes difficult to achieve the downsizing of the wireless device.